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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Guaranteed Monotonic INL Error: 4LSB max On-Chip 1.25/2.5V, 10ppm/C Reference Temperature Range: -40C to +85C Rail to Rail Output Amplifier Package Type: 100-lead LQFP (14mm x 14mm) User Interfaces: Parallel, Serial (SPI, QSPI, Microwire and DSP compatible featuring Data Readback) I2C Compatible Interface INTEGRATED FUNCTIONS Channel Monitor Simultaneous Output Update via LDAC Clear Function to User Programmable Code Amplifier Boost Mode to Optimize Slew Rate User Programmable Offset and Gain Adjust Toggle Mode: Enables Squarewave Generation
40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC AD5380
GENERAL DESCRIPTION
The AD5380 is a complete single supply, 40-channel, 14bit DAC available in 100-lead LQFP package. All 40-channels have an on-chip output amplifier with rail-torail operation. The AD5380 includes an internal 1.25/ 2.5V, 10ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring and an output amplifier boost mode that allows the amplifier settling time to be optimized. The AD5380 contains a double buffered parallel interface featuring a WR pulse width of 20ns, a serial interface compatible with SPITM, QSPITM, MICROWIRETM and DSP interface standards with interface speeds in excess of 30MHz and an I2C compatible interface supporting 400kHz data transfer rate. An input register followed by a DAC register provides double buffering allowing the DAC outputs to be updated independantly or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register allowing the user to fully calibrate any DAC Channel. Power consumption is typically 0.3mA/channel.
APPLICATIONS Variable Optical Attenuators (VOA) Level Setting Optical Microelectromechanical Systems (MEMs) Control Systems FUNCTIONAL BLOCK DIAGRAM
DVDD (X3) PD SER/PAR FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) SDO(A/B) DB13 /(DIN/SDA) DB12 /(SCLK/SCL) DB11 /(SPI/I2C) DB10 . DB0 A5 A0 REG0 REG1 RESET BUSY CLR POWER-ON RESET DGND (X3) AVDD (X5) AGND (X5) DAC GND (X5) REFGND
REFOUT/ REFIN SIGNAL GND (X5)
AD5380
14
INPUT REG 0
2.5V Reference
14
X
m REG0 c REG0
+
14
14 14
FIFO + STATE MACHINE + CONTROL LOGIC
DAC 14 REG 0
DAC 0
+ R R
VOUT 0
INTERFACE CONTROL LOGIC
14
INPUT REG 1
14
14
X
+
. 14 . 14 . . .
14
INPUT REG 6
DAC 14 REG 1
DAC 1 . . . DAC 6
+ R
m REG1
. . . 14 . .X
c REG1
. . . . .
VOUT 1 VOUT 2
R
. . .
+ -
VOUT 3 VOUT 4 VOUT 5 VOUT 6
14 +
14 14
DAC 14 REG 6
m REG6 c REG6
R R
VOUT 0 .......... VOUT 38
14
INPUT REG 7
14
14
X
+
39 -TO-1 MUX
14 14
DAC 14 REG 7
DAC 7
+ R R
VOUT 7 VOUT 8
m REG7 c REG7
X5
LDAC
VOUT 38
VOUT 39 / MON_OUT
*Protected by U.S. Patent Nos. 5,969,657; other patents pending. SPI and QSPI are Trademarks of Motorola, Inc. MICROWIRE is a Trademark of National Semiconductor Corporation. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
4.5V to to 5.5V, AGND=DGND V; C 200 pF to AGND; AD5380-5-SPECIFICATIONS (AV ;=External 5.5V ; DV =2.7Vspecifications T to T= 0 unless=otherwise noted.) R = 5k REFIN=2.5V; All
DD DD L L MIN MAX
Parameter
ACCURACY Resolution Relative Accuracy 3 Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient 2 DC Crosstalk 2 REFERENCEINPUT/OUTPUT REFERENCE INPUT 2 Reference Input Voltage DC Input Impedance Input Current Reference Range REFERENCE OUTPUT 4 Output Voltage Reference TC OUTPUT CHARACTERISTICS 2 Output Voltage Range 3 Short Circuit Current Load Current Capacitive Load Stability RL= RL=5k DC Output Impedance MONITOR PIN Output Impedance Tristate Leakage Current
LOGIC INPUTS (EXCEPT SDA/SCL) 2
AD5380-51
Units
Test Conditions/Comments
14 4 -1/+2 10 10 5 0.02 20 0.5
Bits LSB max LSB max mV max mV max uV/C typ % FSR max ppm FSR/C typ LSBmax
Guaranteed Monotonic Over Temp Measured at code 32 in the linear region
2.5 1 10 1/V DD /2 2.495/2.505 1.248/1.252 10 0/AV DD 40 1 200 TBD 0.5 500 100 2 0.8 10 10
0.7 DV DD 0.3 DVDD 1 A 0.05 DV DD 8 50
V M min A max V min/max V min/max V min/max ppm/C typ V min/max mA max mA max pF max pF max max typ nA typ
1% for Specified Performance Typically 100 M Typically 30 nA At Ambient
DVDD = 2.7 V to 5.5 V V min V max A max pF max
V min V max V pF ns
V IH , Input High Voltage V IL, Input Low Voltage Input Current Pin Capacitance
LOGIC INPUTS (SCL, SDA ONLY) V IH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN , Input Capacitance Glitch Rejection
Total for All Pins. TA=TMIN to TMAX
SMBus-Compatible at DVDD < 3.6 V SMBus-Compatible at DV DD < 3.6 V
Input filtering suppresses noise spikes of less than 50 ns.
LOGIC OUTPUTS (BUSY, SDO)2 V OL, Output Low Voltage V OH, Output High Voltage
V OL, Output Low Voltage V OH, Output High Voltage
0.4 DV DD -1 0.4 DV DD -0.5 1 5
0.4 0.6 1 8
V max V min V max V min A max pF typ
V max V max A pF
High Impedance Leakage Current High Impedance Output Capacitance
LOGIC OUTPUT (SDA) 2 V OL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance
DV DD= 5V 10%, Sinking 200A DV DD= 5V 10%, Sourcing 200 A DV DD = 2.7V to 3.6V, Sinking 200 A DV DD = 2.7V to 3.6V, S o u r c i n g 200 A SDO Only SDO Only
ISINK = 3 mA ISINK = 6 mA
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PRELIMINARY TECHNICAL DATA AD5380
AD5380-5 -SPECIFICATIONS
POWER REQUIREMENTS AV DD DV DD Power Supply Sensitivity 2 Mid Scale/V DD AI DD AI DD DI DD AI DD (Power Down) DI DD (Power Down) Power Dissipation 4.5/5.5 2.7/5.5 -85 0.5 0.57 5 5 5 125
(AVDD = 4.5V to 5.5V ; DVDD=2.7V to 5.5V, AGND=DGND = 0 V; CL = 200 pF to AGND; RL = 5k ; External REFIN=2.5V; All specifications TMIN to TMAX unless otherwise noted.)
V min/max V min/max dB typ mA/Channelmax mA/Channelmax mA max uA max uA max mW max Outputs Unloaded. Boost Off. XXmA typ Outputs Unloaded. Boost On. XXmA typ VIH = DVDD, V IL = DGND. XXmA typ Outputs Unloaded.
NOTES 1 AD5380-5 is calibrated using an external 2.5V reference. Temperature range for All Versions: -40C to +85C 2 Guaranteed by characterization. Not production tested. 3 Accuracy guaranteed from Vout = 10mV to AV DD -50mV 4 Default on the AD5380-5 is 2.5V.Programmable to 1.25V via CR12 in the AD5380 control register but operating the AD5380-5 with a 1.25V reference will lead to degraded accuracy specifications. Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter
(AVDD= 4.5V to 5.5V ; DVDD=2.7V to 5.5V; AGND = DGND= 0 V; CL = 5k and 200 pF to AGND)
All Units Test Conditions/Comments Boost Mode Off, CR11=0 1/4 Scale to 3/4 Scale Change settling to 1LSB. Boost Mode On, CR11=1 1/4 Scale to 3/4 Scale Change settling to 1LSB. Boost Mode Off, CR11=0 Boost Mode On, CR11=1 See Terminology See Terminology Effect of Input Bus Activity on DAC Output Under Test
DYNAMIC PERFORMANCE Output Voltage Settling Time 2 AD5380 Output Voltage Settling Time 2 AD5380 Slew Rate 2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise 0.1 to 10Hz Output Noise Spectral Density @ 1 kHz @ 10 kHz
1 2
8 10 3 5 0.7 1.5 12 5 100 10 10 1 8 150 100
s typ s max s typ s max V/s typ V/s typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ uV p-p typ nV/(Hz) 1/2 typ nV/(Hz)1/2 typ
Guaranteed by design and characterization, not production tested. The Settling Time and Slew Rate can be programmed via the Current Boost Control bit (CR11 ) in the AD5380 Control Register. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
2.7V to C= AD5380-3-SPECIFICATIONS (AV ;=External 3.6V ; DV =2.7V to 5.5V, AGND=DGNDto=T 0 V;unless 200 pF to AGND; R = 5k REFIN=1.25V; All specifications T otherwise noted.)
DD DD L L MIN MAX
Parameter
ACCURACY Resolution Relative Accuracy 3 Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient 2 DC Crosstalk 2 REFERENCEINPUT/OUTPUT REFERENCE INPUT 2 Reference Input Voltage DC Input Impedance Input Current Reference Range REFERENCE OUTPUT 4 Output Voltage Reference TC OUTPUT CHARACTERISTICS 2 Output Voltage Range 3 Short Circuit Current Load Current Capacitive Load Stability RL= RL=5k DC Output Impedance MONITOR PIN Output Impedance Tristate Leakage Current
LOGIC INPUTS (EXCEPT SDA/SCL) 2
AD5380-31
Units
Test Conditions/Comments
14 4 -1/+2 10 10 5 0.02 20 0.5
Bits LSB max LSB max mV max mV max uV/C typ % FSR max ppm FSR/C typ LSBmax
Guaranteed Monotonic Over Temp Measured at code 64 in the linear region
1.25 1 10 1 to AVDD/2 1.248/1.252 2.495/2.505 10 0/AV DD 40 1 200 TBD 0.5 500 100 2 0.8 10 10
0.7 DV DD 0.3 DVDD 1 A 0.05 DV DD 8 50
V M min A max V min/max V min/max V min/max ppm/C typ V min/max mA max mA max pF max pF max max typ nA typ
1% for Specified Performance Typically 100 M Typically 30 nA At Ambient
DVDD = 2.7 V to 3.6V V min V max A max pF max
V min V max V pF ns
V IH , Input High Voltage V IL, Input Low Voltage Input Current Pin Capacitance
LOGIC INPUTS (SCL, SDA ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN , Input Leakage Current VHYST , Input Hysteresis CIN , Input Capacitance Glitch Rejection
Total for All Pins. TA=TMIN to TMAX
SMBus-Compatible at DVDD < 3.6 V SMBus-Compatible at DV DD < 3.6 V
Input filtering suppresses noise spikes of less than 50 ns.
LOGIC OUTPUTS (BUSY, SDO)2 V OL, Output Low Voltage V OH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance
LOGIC OUTPUT (SDA) 2 V OL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance
0.4 DV DD -0.5 1 5
0.4 0.6 1 8
V max V min A max pF typ
V max V max A pF
Sinking 200A Sourcing 200A SDO Only SDO Only
ISINK = 3 mA ISINK = 6 mA
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PRELIMINARY TECHNICAL DATA AD5380
AD5380-3-SPECIFICATIONS
POWER REQUIREMENTS AV DD DV DD Power Supply Sensitivity 2 Mid Scale/V DD AI DD AI DD DI DD AI DD (Power Down) DI DD (Power Down) Power Dissipation 2.7/3.6 2.7/3.6 -85 0.5 0.57 5 5 5 125
(AVDD = 2.7V to 3.6V ; DVDD=2.7V to 5.5V, AGND=DGND = 0 V; CL = 200 pF to AGND; RL = 5k ; External REFIN=1.25V; All specifications TMIN to TMAX unless otherwise noted.)
V min/max V min/max dB typ mA/Channelmax mA/Channelmax mA max uA max uA max mW max Outputs Unloaded. Boost Off. XXmA typ Outputs Unloaded. Boost On. XXmA typ VIH = DVDD, VIL = DGND. XXmA typ Outputs Unloaded.
NOTES 1 AD5380-3 is calibrated using an external 1.25V reference. Temperature range is -40C to +85C. 2 Guaranteed by characterization. Not production tested. 3 Accuracy guaranteed from Vout = 10mV to AV DD -50mV 4 Default on the AD5380-3 is 1.25V. Programmable to 2.5V via CR12 in the AD5380 control register but operating the AD5380-3 with a 2.5V reference will lead to degraded accuracy specifications and limited input code range. Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter
(AVDD= 2.7V to 3.6V ; DVDD=2.7V to 5.5V; AGND = DGND= 0 V; CL = 5k and 200 pF to AGND)
All Units Test Conditions/Comments Boost Mode Off, CR11=0 1/4 Scale to 3/4 Scale Change settling to 1LSB. Boost Mode On, CR11=1 1/4 Scale to 3/4 Scale Change settling to 1LSB. Boost Mode Off, CR11=0 Boost Mode On, CR11=1 See Terminology See Terminology Effect of Input Bus Activity on DAC Output Under Test
DYNAMIC PERFORMANCE Output Voltage Settling Time 2 AD5380 Output Voltage Settling Time 2 AD5380 Slew Rate 2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise 0.1 to 10Hz Output Noise Spectral Density @ 1 kHz @ 10 kHz
1 2
8 10 3 5 0.7 1.5 12 5 100 10 10 1 8 150 100
s typ s max s typ s max V/s typ V/s typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ uV p-p nV/(Hz) 1/2 typ nV/(Hz)1/2 typ
Guaranteed by design and characterization, not production tested. The Settling Time and Slew Rate can be programmed via the Current Boost Control bit (CR11 ) in the AD5380 Control Register. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA TIMING CHARACTERISTICS
SERIAL INTERFACE
(DVDD= 2.7V to 5.5V ; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; ) All specifications TMIN to TMAX unless otherwise noted.) Units ns ns ns ns min min min min Description SCLK Cycle Time SCLK High Time SCLK Low Time SYNC Falling Edge to SCLK Falling Edge Setup Time 24th SCLK Falling Edge to SYNC Falling Edge Minimum SYNC Low Time Minimum SYNC High Time Minimum SYNC High Time in Readback Mode Data Setup Time Data Hold Time 24th SCLK Falling Edge to BUSY Falling Edge BUSY Pulse Width Low (Single Channel Update) 24th SCLK Falling Edge to LDAC Falling Edge LDAC Pulse Width Low BUSY Rising Edge to DAC Output Response Time BUSY Rising Edge to LDAC Falling Edge LDAC Falling Edge to DAC Output Response Time DAC Output Settling Time, Boost Mode off. CLR Pulse Width Low CLR Pulse Activation Time SCLK Rising Edge to SDO Valid SCLK Falling Edge to SYNC Rising Edge SYNC Rising Edge to SCLK Rising Edge SYNC Rising Edge to LDAC Falling Edge
Parameter1,2,3 t1 t2 t3 t4 t54 t64 t7 t7A t8 t9 t 104,5 t11 t124 t13 t14 t15
t 16
Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.5 30 900 20 20 100 0
100
ns min ns min ns min ns min ns min ns min ns max ns typ ns min ns min ns max ns min
ns min
t17 t18 t19 t 206,7 t217 t227 t237
8 20 12 20 5 8 20
s typ ns min s max ns max ns min ns min ns min
NOTES 1 Guaranteed by design and characterization, not 2 All input signals are specified with tr = tf = 5 ns 3 See Figures 3 and 4 4 Stand-Alone Mode only. 5 This is measured with the load circuit of Figure 6 This is measured with the load circuit of Figure 7 Daisy-Chain Mode only. Specifications subject to change without notice.
production tested. (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
1a. 1b.
VCC
RL 2.2k
TO O UTP UT P IN
200u A
IO L
TO OUTPUT PIN
CL 50pF
VOL
CL 50pF 200u A IO H
V O H (M IN) or V O L (M A X )
Figure 1a Load Circuit for BUSY Timing Diagram
Figure 1b. Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain mode)
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PRELIMINARY TECHNICAL DATA AD5380
t1 SCLK 1 t4 SYNC t7 t8 DIN DB23 t6 t9 DB0 t10 BUSY t12 LDAC1 VOUT1 LDAC2 VOUT2 t18 CLR t19 V OUT
1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY
2 t3 t2
24 t5
24
t11 t13 t14 t17 t15 t13
t16 t17
Figure 3. Serial Interface Timing Diagram (Stand-Alone mode)
SCLK
24 t 7A
48
SYNC
DIN
DB23 Input Word Specifies Register to be Read
DB0
DB23' NOP Condition DB23
DB0'
SDO UNDEFINED
DB0 Selected Register Data Clocked out.
Figure 3a. Serial Interface Timing in Data Readback Mode
t1 t1 SCLK t7 t4 SYNC t8 t9 DIN DB23 Input Word for DAC N SDO UNDEFINED LDAC DB0 DB23' Input Word for DAC N+1 t20 DB23 Input Word for DAC N DB0 t23 t13 DB0' t3 t2 t21 24 48 t22
Figure 4. Serial Interface Timing Diagram (Daisy-Chain mode)
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PRELIMINARY TECHNICAL DATA AD5380 TIMING CHARACTERISTICS
I2C SERIAL INTERFACE
(DVDD= 2.7V to 5.5V ; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; ) All specifications TMIN to TMAX unless otherwise noted.) Units
kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max
Parameter1,2 Limit at TMIN, TMAX
F SCL t1 t2 t3 t4 t5 t63 t7 t8 t9 t 10 t 11 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1Cb4 400
Description
SCL Clock Frequency SCL Cycle Time t HIGH, SCL High Time tLOW, SCL Low Time t HD,STA, Start/Repeated Start Condition Hold Time tSU,DAT, Data Setup Time t HD,DAT, Data Hold Time t HD,DAT, Data Hold Time tSU,STA, Setup Time for Repeated Start tSU,STO, Stop Condition Setup Time tBUF, Bus Free Time Between a STOP and a START Condition tR, Rise Time of SCL and SDA when Receiving tR, Rise Time of SCL and SDA when Receiving (CMOS-Com patible) tF, Fall Time of SDA when Transmitting t F, Fall Time of SDA when Receiving (CMOS-Compatible) tF, Fall Time of SCL and SDA when Receiving tF, Fall Time of SCL and SDA when Transmitting Capacitive Load for Each Bus Line
CB
NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Figure 5 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH MIN of the SCL signal) in order to bridge the undefined region of SCL's falling edge. 4 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t 10
t 11
t4
SCL
t4
START CONDITION
t6
t2 t5 t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
Figure 5. I2C Compatible Serial Interface Timing Diagram
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PRELIMINARY TECHNICAL DATA AD5380 TIMING CHARACTERISTICS
PARALLEL INTERFACE
(DVDD = 2.7 V to +5.5V; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND = DGND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min min min min min min min min min min max max min min max min min min Description REG0,REG1,Address to WR Rising Edge Setup Time REG0,REG1, Address to WR Rising Edge Hold Time CS Pulse Width Low WR Pulse Width Low CS to WR Falling Edge Setup Time WR to CS Rising Edge Hold Time Data to WR Rising Edge Setup Time Data to WR Rising Edge Hold Time WR Pulse Width High Minimum WR Cycle Time (Single Channel Write) WR Rising Edge to BUSY Falling Edge BUSY Pulse Width Low (Single Channel Update) WR Rising Edge to LDAC Falling Edge LDAC Pulse Width Low BUSY Rising Edge to DAC Output Response Time LDAC Rising Edge to WR Rising Edge BUSY Rising Edge to LDAC Falling Edge LDAC Falling Edge to DAC Output Response Time DAC Output Settling Time, Boost Mode Off. CLR Pulse Width Low CLR Pulse Activation Time
Parameter 1,2,3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t94 t 10 4 t 11 4,5 t 12 4 t 13 t 14 4 t 15 t 16 t 17 4 t 18 t 19 t 20
Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.5 20 430 30 400 30 20 100 20 0 100 8 20 12
s typ
ns min
s max
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See Timing Diagram in Figure 6. 4 See Table XXX. 5 This is measured with the load circuit of Figure 1a. Specifications subject to change without notice. t0 t1
REG0, REG1, A5..A0 t4 CS WR t2 t3 t6 DB13..DB0 t10 BUSY t12 LDAC1 VOUT1 LDAC2 VOUT2 t19 CLR t20 VOUT
1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY
t5 t9 t8 t7 t15
t11 t13 t14 t18 t16 t13
t17 t18
Figure 6. Parallel Interface Timing Diagram
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PRELIMINARY TECHNICAL DATA AD5380
ABSOLUTE MAXIMUM RATINGS1,2
(TA = +25C unless otherwise noted)
AVDD to AGND...............................................-0.3 V to +7 V DVDD to DGND..............................................-0.3 V to +7 V Digital Inputs to DGND............-0.3 V to DVDD + 0.3 V SDA/SCL to DGND..............................-0.3 V to + 7 V Digital Outputs to DGND..........-0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND......-0.3 V to AVDD + 0.3 V AGND to DGND................................-0.3 V to +0.3 V VOUT0-39 to AGND............... - 0.3 V to AVDD + 0.3 V Analog Inputs to AGND............ - 0.3 V to AVDD + 0.3 V
Operating Temperature Range Commercial (B Version).......................-40C to +85C Storage Temperature Range...................-65C to +150C JunctionTemperature (T J max).............................+150C 100-lead LQFP Package, JA ThermalImpedance.....................................44C/W Reflow Soldering Peak Temperature......................................................230C NOTES:
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100mA will not cause SCR latch-up
ORDERING GUIDE
Model Option
Resolution
AV DD Range +4.5V to +5.5V +2.7V to +3.6V
Output Channels
40 40
Linearity Package Error (LSBs)
Package Description
AD5380BST-5 14-Bits AD5380BST-3 14-Bits Eval-AD5380EB
4 4
100-lead LQFP ST-100 100-lead LQFP ST-100 AD5380 Evaluation Kit
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5380 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA AD5380
PIN CONFIGURATIONS AD5380 (40-CHANNEL, 14-BIT)
98 DB12/(SCLK/SCL) 100 CS/(SYNC/AD0) 99 DB13/(DIN/SDA) 97 DB11/(SPI/I2C) 78 WR (DCEN/AD1) 77 LDAC 94 DB8 93 SDOUT(A/B)
80 SER/PAR
92 DVDD
91 DGND 90 DGND
84 A0 83 DVDD
82 DVDD
81 DGND
76 BUSY
96 DB10 95 DB9
89 A5 88 A4
79 PD
87 A3
86 A2 85 A1
FIFO EN CLR VOUT 24 VOUT 25 VOUT 26 VOUT 27 SIGNAL_GND4 DAC_GND4 AGND4
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
75 RESET 74 DB7 73 DB6 72 DB5 71 DB4 70 DB3 69 DB2 68 DB1 67 DB0 66 REG0 65 REG1
AVDD4 10 VOUT 28 11 VOUT 29 12 VOUT 30 13 VOUT 31 14 REF GND 15 REFOUT/REFIN 16 SIGNAL_GND1 17 DAC_GND1 18 AVDD1 19 VOUT 0 20 VOUT 1 21 VOUT 2 22 VOUT 3 23 VOUT 4 24 AGND1 25
SIGNAL_GND5 26 DAC_GND5 27 AGND5 28 AVDD5 29 VOUT5 30 VOUT 32 33 VOUT 33 34 VOUT 6 31 VOUT 7 32 VOUT 36 37 VOUT 37 38 VOUT 38 39 VOUT 39/MON_ OUT 40 DAC_GND2 46 SIGNAL_GND2 47 VOUT 14 49 VOUT 15 50 VOUT 34 35 VOUT 35 36 VOUT 8 41 VOUT 9 42 VOUT 10 43 VOUT 11 44 VOUT 12 45 VOUT 13 48
AD5380
TOP VIEW (Not to Scale)
64 VOUT 23 63 VOUT 22 62 VOUT 21 61 VOUT 20 60 AVDD3 59 AGND3 58 DAC_GND3 57 SIGNAL_GND3 56 VOUT 19 55 VOUT 18 54 VOUT 17 53 VOUT 16 52 AVDD2 51 AGND2
AD5380 PIN FUNCTION DESCRIPTIONS
Mnemonic VOUTX
Function Buffered analog outputs for channel X. Each analog output is driven by a rail to rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5k to ground. Typical output impedance is 0.5 ohms. Analog ground reference points for each group of 8 output channels. All signal_gnd pins are tied together internally and should be connected to AGND plane as close as possible to the AD5380. Each group of 8 channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs.These pins shound be connected to the AGND plane. Analog Ground reference point. Each group of 8 channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. Analog Supply pins. Each group of 8 channels has a separate AVDD pin. These pins should be decoupled with 0.1uF ceramic capacitors and 10uF tantalum capacitors. Operating range for the ASD5380-5 is 4.5V to 5.5V and for the AD5380-3 is 2.7V to 3.6V Ground for all digital circuitry. Logic Power Supply; Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with 0.1uF ceramic and 10uF tantalum capacitors to DGND. Ground Reference point for the internal reference. The AD5380 contains a common REFOUT/REF IN pin. When the internal reference is selected this pin is the reference output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled vis the control register. The default for this pin is a reference input. -11-
SIGNAL_GND(1-5)
DAC-GND (1-5) AGND (1-5) AVDD (1-5)
DGND DVDD REF-GND REFOUT/REFIN
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PRELIMINARY TECHNICAL DATA AD5380
VOUT39/MON_OUT This pin has a dual function, it acts a a buffered output for channel 39 in default mode but when the monitor function is enabled this output acts as the output of a 39-to-1 channel multiplexer which can be programmed to multiplex one of channels 0 to 38 to the MON_OUT pin. The MON_OUT pins output impedance is typically 500 ohms and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. Interface Select Input. This pin allows the user to select whether the serial or parallel interface will be used. If it is tied high the serial interface mode is selected and pin 97 (SPI/ I2C) is used to determine if the interface mode is SPI or I2C. Parallel interface mode is selected when SER/PAR is low. In parallel interface mode this pin acts as Chip Select Input (level sensitive, active low). When low the AD5380 device is selected. Serial Interface Mode: This is the Frame Synchronisation input signal for the serial interface. When taken low the internal counter is enabled to count the required number of clocks before the addressed register is updated. I2C Mode: This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address for the device on the I2C bus. Multi Function pin. In parallel interface mode acts as Write enable and in serial interface mode acts as a daisy chain enable in SPI mode and as a hardware address pin in I2C mode. Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low and the address bus inputs to write to the selected device registers. Serial Interface: Daisy-Chain Select Input (level sensitive, active high). When high this signal is used in conjunction with SER/PAR high to enable SPI serial interface daisy-chain mode. I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. Parallel Data Bus. DB13 is the MSB and DB0 is the LSB of the input data word on the AD5380 Parallel Address Inputs. A5 to A0 are decoded to address one of the 40 input channels on the AD5380. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register or gain register for the selected channel and also are used to decide the special function registers. Serial Data Output in serial interface mode. Tristatable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. When operating in parallel interface mode this pin acts as the A or B data register select when writing data to the AD5380 data registers when toggle mode is selected (See Toggle Mode Function). In toggle mode the LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels contain two data registers. In normal mode data register A is the default for data transfers. Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time the user can continue writing new data to further x1, c and m registers (these are stored in a FIFO) but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low this event is stored. BUSY also goes low during power-on-reset and when the RESET pin is low. During this time the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high) the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However any events on LDAC during power-on-reset or RESET are ignored. Asynchronous Clear Input (level sensitive, active low). While CLR is low all LDAC pulses are ignored. When CLR is activated all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 12us while all channels are being updated with the CLR code. Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the Power-On-Reset generator. When this pin is taken low, the statemachine initiates a reset sequence to digitally reset x1, m, c, and x2 registers to their default -12- REV. PrF 09/2003
SER/ PAR.
CS/( SYNC/AD0)
WR /(DCEN/AD1)
DB13-DB0 A5-A0
REG1,REG0
SDOUT/(A/B)
BUSY
LDAC
CLR
RESET
PRELIMINARY TECHNICAL DATA AD5380
power-on values. This sequence takes 300us (typ). The falling edge of RESET initiates the RESET process and BUSY goes low for the duration returning high when RESET is complete. While BUSY is low all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high the part resumes normal operation and the status of the RESET pin is ignored till the next falling edge is detected. Power Down (level sensitive active high). Used to place the device in low power mode where the device consumes less than 5uA. In power pown mode all internal analog circuitry is placed in low power mode, the analog output will be configured as high impedance outputs or will provide a 100k load to ground depending on how the power down mode is configured. The serial interface remains active during power down. FIFO Enable (level sensitive active high). When connected to DVCC the internal FIFO is enabled allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO_EN pin is sampled on power-up, and also following a CLEAR or RESET to determine if the FIFO is enabled. In either serial or I2C interface modes the FIFO_EN pin shpould be tied low. Multi-function input pin. In parallel interface mode this pin acts as DB11 of the parallel input data word. In serial interface mode this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR =1) and this input is low I2C Mode is selected. In this mode DB12 is the serial clock (SCLK) input and DB13 is the serial data (DIN) input. When serial interface mode is selected (SER/PAR =1) and this input is high SPI Mode is selected. In this mode DB12 is the serial clock (SCL) input and DB13 is the serial data (SDA) input. Multi-function input pin. In parallel interface mode this pin acts as DB12 of the parallel input data word. In serial interface mode this pin acts as a serial clock input. Serial Interface Mode: In serial interface mode data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 50 MHz. I2C Mode: In I2C mode this pin performs the SCL function, clocking data into the device. Data transfer rate in I2C mode is compatible with both 100kHz and 400kHz operating modes. Multi-function data input pin. In parallel interface mode this pin acts as DB13 of the parallel input data word. Serial Interface Mode: In serial interface mode this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. I2C Mode: In I2C mode this pin is the serial Data pin (SDA) operating as an open drain input/output.
PD
FIFO_EN
DB11 (SPI/I2C)
DB12 (SCLK/SCL)
DB13/(DIN/SDA)
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PRELIMINARY TECHNICAL DATA AD5380
TERMINOLOGY Relative Accuracy DC Output Impedance
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in Least Significant Bits.
Differential Nonlinearity
This is the effective output source resistance. dominated by package lead resistance.
Output Voltage Settling Time
It is
This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and measured from BUSY rising edge.
Digital-to-Analog Glitch Energy
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Zero-Scale Error
This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFF Hex and 2000Hex.
DAC-to-DAC Crosstalk
Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2 n-1 : VOUT (Zero-Scale) = 0V Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It is mainly due to offsets in the output amplifier. Offset-Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5380-5 with Code 32 loaded into the DAC register and with code 64 on the AD5380-3.
Gain Error
DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one DAC output due to both the digital change and subsequent analog O/P change at another DAC. The victim channel is loaded with midscale and DAC-to-DAC crosstalk is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
Gain Error is specified in the linear region of the ouput range between Vout =10mV and Vout =AVdd-50mV. It is the deviation in slope of the DAC transfer characteristic from ideal and is expressed in % FSR with the DAC output unloaded.
DC Crosstalk
When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough.
Output Noise Spectral Density
This is the DC change in the output level of one DAC at midscale in response to a fullscale code (all 0's to all 1's and vice versa) and output change of all other DACs. It is expressed in lsbs.
This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(Hz)1/2 in a 1 Hz bandwidth at 10KHz.
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PRELIMINARY TECHNICAL DATA AD5380 AD5380-5 Typical Performance Characteristics
AD5380 Typical INL Plot
AD5380 Typical DNL Plot
AD5380 Power-Up Transient
AD5380 Glitch Energy
AD5380 Slew Rate with Boost Off
AD5380 Slew Rate with Boost On
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PRELIMINARY TECHNICAL DATA AD5380 Typical Performance Characteristics
2* Idd Histograms INL/DNL Vs Vref INL /DNL Distributions Offset error distribution Fullscale error distribution Output Spectral Density Vs Frequency Source and Sink Capability DAC-DAC crosstalk 0.1 to 10Hz noise plot
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PRELIMINARY TECHNICAL DATA AD5380
FUNCTIONAL DESCRIPTION DAC Architecture -- General
The AD5380 is a complete single supply, 40-channel, voltage output DAC offering 14-bit resolution, available in a 100 lead LQFP package and features both a parallel and serial interfaces. This family includes an internal 1.25/2.5V, 10ppm/C reference that can be used to drive the buffered reference inputs, alternatively an external reference can be used to drive these inputs. Reference selection is via a bit in the control register. All channels have an on-chip output amplifier with rail-to-rail output capable of driving a 5k ohm in parallel with a 200pf load. The architecture of a single DAC channel consists of a 14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of two. This resistor-string architecture guarantees DAC monotonicity. The 14-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independant offset and gain control registers allowing the user to digitally trim offset and gain. The inclusion of these registers allows the user the ability
x2 is the Dataword loaded to the resistor string DAC VREF is the reference voltage applied to the DAC, 2.5V for specified performance. Data Decoding The AD5380 contains a 14-bit data bus, DB13-DB0. Depending on the value of REG1 and REG0 outlined in Table 1, this data is loaded into the addressed DAC input register(s), Offset (c) register(s), or Gain (m) register(s). The format data, Offset (c) and gain (m) register contents are outlined in tables II to IV.
Table I. Register Selection
REG1 REG0 1 1 0 0 1 0 1 0
Register Selected Input Data Register (x1) Offset Register (c) Gain Register (m) Special Function Registers (SFRs)
VREF x1 INPUT REG INPUT DATA m REG c REG x2 DAC REG 14-BIT DAC + -
AVDD
Table II. DAC Data format (REG1 = 1, REG0 = 1)
DB13 to DB0
VOUT R
DAC Output 2 VREF x (16383/16384) V 2 VREF x (16382/16384)V 2 VREF x (8193/16384) V 2 VREF x (8192/16384) V 2 VREF x (8191/16384) V 2 VREF x (1/16384) V 0 V
R
11 1111 11 1111 10 0000 10 0000 01 1111 00 0000 00 0000
1111 1111 0000 0000 1111 0000 0000
1111 1110 0001 0000 1111 0001 0000
Figure 7. Single Channel Architecture
to calibrate out errors in the complete signal chain including the DAC using the internal M and C registers which hold the correction factors. All channels are double buffered allowing synchronous updating of all channels using the LDAC pin. Figure 7 shows a block diagram of a single channel on the AD5380. The digital input transfer function for each DAC can be represented as: x2 = [(m + 1 )/8192 x x1] + (c-2n-1) x2 is the Dataword loaded to the resistor string DAC x1 is the 14-bit Dataword written to the DAC input register. m is the13-bit Gain Coefficient (default is all 1FFF Hex on the AD5380. The gain coefficient is written to the 13 most significant bits. If a 14 bit data word is provided to the m register the lsb of the data word will be a zero. n=DAC resolution (n=14 for AD5380) c is the14-bit Offset Coefficient (default is 2000Hex on the AD5380) The complete transfer function for these devices can be represented as: VOUT = 2 x VREF x x2/2n REV. PrF 09/2003 -17-
Table III. Offset Data format (REG1 = 1, REG0 = 0)
DB13 to DB0 11 11 10 10 01 00 00 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1110 0001 0000 1111 0001 0000
Offset +8191LSB +8190LSB +1 LSB +0 LSB -1 LSB -8191 L S B -8192 L S B
Table IV. Gain Data format (REG1 = 0, REG0 = 1)
DB13 to DB1 1 1 0 0 0 1111 0111 1111 0111 0000 1111 1111 1111 1111 0000 1111 1111 1111 1111 0000
Gain Factor 1 0.75 0.5 0.25 0
PRELIMINARY TECHNICAL DATA AD5380
AD5380 On-chip Special Function Registers (SFR) The AD5380 contains a number of special function registers (SFRs)as outlined in table V. SFRs are addressed with REG1=REG0= 0 and are decoded using the Address bits A5 to A0.
Table V. SFR Register Functions (REG1 =0, REG0 = 0)
R / W A5 A4 A3 A2 A1 X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1
A0 0 1 0 0 1 0 0 0 1
Function NOP (No Operation) Write ClR Code Soft CLR Soft Power Down Soft Power Up Control Register Write Control Register Read Monitor Channel Soft Reset
SFR Commands NOP (no operation) REG1=REG0=0, A5-A0=000000 Performs no operation but is useful in readback mode to clock out data on Dout for diagnostic purposes. BUSY pulses low during a NOP operation. Write CLR Code REG1=REG0=0, A5-A0=000001 DB13-DB0= Contain the CLR data. Bringing the CLR line low or exercising the soft clear function will load the contents of the DAC registers with the data contained in the user configurable CLR register and sets VOUT0-VOUT39 accordingly. This can be very useful not only for setting up a specific output voltage in a clear condition but can also be used for calibration purposes where the user can load fullscale or zeroscale to the the clear code register and then issue a hardware or software clear to load this code to all DAC removing the need for individual writes to all DACs. Default on power up is all zeroes. Soft CLR REG1=REG0=0, A5-A0=000010 DB13-DB0= Dont Care. Executing this instruction performs the CLR which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. The time taken to fully execute the SOFT CLR is 80*400ns and is indicated by the BUSY low time. Soft Power Down REG1=REG0=0, A5-A0=001000 DB13-DB0= Dont Care. Executing this instruction performs a global power-down feature that puts all channels into a low power mode reducing both analog and digital power consumption to 5uA. In power down mode the output amplifier can be configured as a high impedance output or provide a 100k load to ground. The contents of all internal registers are retained in powerdown mode. Cannot write to any register while in power down. Soft Power up REG1=REG0=0, A5-A0=001001 DB13-DB0= Dont Care. This instruction is used to power up the output amplifiers and internal reference. The time to exit power down is XXus. The hardware power down and software function are internally combined in a digital OR function. Soft RESET REG1=REG0=0, A5-A0=001111 DB13-DB0= Dont Care. This instruction is used to implement a software reset. All internal registers are reset to their default values which corresponds to m at fullscale and c at zero. The contents of the DAC registers are cleared setting all analog outputs to zero volts. The soft reset activation time is 150us (typ).
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PRELIMINARY TECHNICAL DATA AD5380
Control Register Write/Read REG1=REG0=0, A5-A0=001100, R/W status determines if the operation is a write (R/W=0) or a read (R/W=1). DB13-DB0 contains the control register data. AD5380 Control Register Contents MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0
Table VI: AD5380 Control Register Contents CR13: Power Down Status. This bit is used to configure the output amplifier state in power down. CR13=1 amplifier output is high impedance . CR13=0 amplifier output is 100k to ground (default on power up). CR12: REF Select. This bit selects the operating internal reference for the AD5380. CR12 is programmed as follows: CR12=1: Internal reference is 2.5V (AD5380-5 default). Recommended operating reference for AD5380-5. CR12=0: Internal reference is 1.25V (AD5380-3 default). Recommended operating reference for AD5380-3. CR11: Current Boost Control. This bit is used to boost the current in the output amplifier therby altering its slew rate. This bit is configured as follows: CR11=1: Boost mode on. This maximizes the bias current in the output amplifier optimizing its slew rate but increasing the power dissipation. CR11=0: Boost mode off (default on power up). This reduces the bias current in the output amplifier and reduces the overall power consumption. CR10: Internal/External Reference. This bits determines if the DAC uses its internal reference or an externally applied reference. CR10=1: Internal Reference enabled. Reference output depends on data loaded to CR12. CR10=0: External Reference selected (default on power up) CR9: Channel Monitor Enable (see channel monitor function ) CR9=1: Monitor Enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register the selected channel output is routed to the MON_OUT pin. VOUT 39 operates as the MON-OUT pin on the AD5380. CR9=0: Monitor Disabled (default on power-up). When monitor is disabled the MON_OUT pin assumes its normal DAC output function on the AD5380. CR8: Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5380 when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130 degree C. This function can be used to protect the device in cases where the power dissipation of the device may be exceeded if a number of output channels are simultaneously short circuited. A soft power-up will re-enable the output amplifiers id the die temperature has dropped below 130C. CR8=1: Thermal monitor enabled. CR8=0 Thermal monitor disabled (default on power-up). CR7: Dont Care CR6 to CR2: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A and B register for each DAC. Control Register bits CR6 to CR2 are used to enable individual groups of 8-channels for operation in toggle mode. A logic 1 written to any bit enables a group of channels and a logic zero disables a group. LDAC is used to toggle between the two registers. Logic 1 enables a group of channels and a logic zero disables a group. CR Bit Group Channels CR1 and CR0 are dont cares. CR6 4 32-39 CR5 3 24-31 CR4 2 16-23 CR3 1 8-15 CR2 0 0-7
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PRELIMINARY TECHNICAL DATA AD5380
Channel Monitor Function REG1=REG0=0, A5-A0=001010 DB13-DB8= Contain data to address the channel to be monitored. A monitor function is provided on all devices. This feature consisting of a multiplexer addressed via the interface allows any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode Vout 39 becomes the MON_OUT pin, the pin to which all monitored pins are routed. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. On the AD5380, DB13 to DB8 contain the channel address for the monitored channel. Selecting channel address 63 tristates the MON_OUT pin. The Channel Address decoding for the AD5380 is as follows: REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 REG0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 A4 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . 1 1 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . 1 1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . 0 0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 ->DB0 AD5380 MON_OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 . . 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 . . 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 . . 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 . . 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 . . 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 . . 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X . . X X Vout 0 Vout 1 Vout 2 Vout 3 Vout 4 Vout 5 Vout 6 Vout 7 Vout 8 Vout 9 Vout 10 Vout 11 Vout 12 Vout 13 Vout 14 Vout 15 Vout 16 Vout 17 Vout 18 Vout 19 Vout 20 Vout 21 Vout 22 Vout 23 Vout 24 Vout 25 Vout 26 Vout 27 Vout 28 Vout 29 Vout 30 Vout 31 Vout 32 Vout 33 Vout 34 Vout 35 Vout 36 Vout 37 Vout 38 Undefined . . Undefined Tristate
Table X. AD5380 Channel Monitor Decoding
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PRELIMINARY TECHNICAL DATA AD5380
REG1 REG0 A5 A4 A3 A2 A1 A0
00001010 VOUT 0 VOUT 1 . . . . . VOUT 37 VOUT 38
AD5380 CHANNEL MONITOR DECODING
VOUT 39/MON_OUT
CHANNEL ADDRESS
DB13-DB8
Figure 8. AD5380 Channel Monitor Decoding
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PRELIMINARY TECHNICAL DATA AD5380
HARDWARE FUNCTIONS Reset Function
Bringing the RESET line low resets the contents of all internal registers to their power-on-reset state. Reset is a negative edge sensitive input. The default corresponds to m at fullscale and c at zero. The contents of the DAC registers are cleared setting VOUT0-VOUT39 to zero volts. This sequence takes 300us (typ). The falling edge of RESET initiates the reset process and BUSY goes low for the duration returning high when RESET is complete. While BUSY is low all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high the part resumes normal operation and the status of the RESET pin is ignored till the next falling edge is detected.
Asynchronous Clear Function
Bringing the CLR line low clears the contents of the DAC registers to the data contained in the user configurable CLR register and sets VOUT0-VOUT39 accordingly. This function can be used in system calibration to load zeroscale and fullscale to all channels together.The execution time for a CLR is 32us.
BUSY and LDAC Functions
BUSY is a digital cmos output indicating the status of the AD5380 device. The value of x2 (x2 is the internal data loaded to the DAC data register) is calculated each time the user writes new data to the corresponding x1, c or m registers. During the calculation of x2 the BUSY output goes low. While BUSY is low the user can continue writing new data to the x1, m or c registers but no DAC output updates can take place. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. The user may hold the LDAC input permanently low and in this case the DAC outputs update immediately after BUSY goes high. BUSY also goes low during power-on-reset and when a falling edge is detected on the RESET pin . During this time all interfaces are disabled and any events on LDAC are ignored. The AD5380 contains an extra feature whereby a DAC register is not updated unless it's x2 register has been written to sincethe last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However the AD5380 will only update the DAC register if the x2 data has changed, thereby removing unnecessary digital crosstalk. FIFO Operation in Parallel mode The AD5380 contains a FIFO to optimize operation when operating in parallel interface mode. The FIFO Enable (level sensitive active high)is uesed to enable the internal FIFO. When connected to DVCC the internal FIFO is enabled allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO_EN pin is sampled on power-up, and also following a CLEAR or RESET to determine if the FIFO is enabled. In either serial or I2C interface modes the FIFO_EN pin shpould be tied low. Up to 128 successive intructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full any further writes to the device are ignored. Figure 9 shows a comparisson between FIFO mode and non-FIFO mode in terms of channel update time, diguial loading time is also outlined in this graph.
2.50E-05
2.00E-05
Without FIFO (Channel update time) With FIFO (Channel update time) With FIFO (digital loading time)
1.50E-05
Time
1.00E-05 5.00E-06 0.00E+00 1 4 7 10 13 16 19 22 25 28 31 34 37 40
Number of Writes
Figure 8. Channel Update Rate (FIFO vs NON-FIFO)
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PRELIMINARY TECHNICAL DATA AD5380
Power-On-Reset
The AD5380 contains a power-on-reset generator and state-machine. The power-on-reset resets all registers to a predefined state and the analog outputs are configured with a 100k impedance to ground. The BUSY pin goes low during the power-on-reset sequencing preventing data writes to the device.
Power-Down
The AD5380 contains a global power-down feature that puts all channels into a low power mode reducing both analog and digital power consumption to 5uA. In power down mode the output amplifier can be configured as a high impedance output or provide a 100k load to ground. The contents of all internal registers are retained in power-down mode. When exiting power down the settling time of the amplifier will elapse before the outputs settle to their correct value. AD5380 INTERFACES The AD5380 contains both a parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either DSP,SPI,MICROWIRE or I2C compatible. The SER/PAR pin selects parallel and serial interface modes. In serial mode SPI/I2C pin is used to select DSP,SPI,MICROWIRE or I2C interface mode. The devices use an internal FIFO memory to allow high speed successive writes in parallel interface mode. The user can continue writing new data to the device while write instructions are being executed. The BUSY signal indicates the current status of the device, going low while instructions in the FIFO are being executed. Up to 128 successive intructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full any further writes to the device are ignored. To minimize both the power consumption of the device and on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e. on the falling edge of WR or on the falling edge of SYNC.
DSP, SPI, MICROWIRE COMPATIBLE SERIAL INTERFACES
The serial interface can be operated with a minimum of 3-wires in stand alone mode or 4-wires in daisy chain mode. Daisy chaining allows many devices to be cascaded together to increase system channel count.The SER/PAR pin must be tied high and the SPI/I2C (pin 97) should be tied high to enable the DSP,SPI,MICROWIRE compatible serial interface. In serial interface mode the user does not need to drive the parallel input data pins. The serial interface is control pins are as follows: SYNC, SYNC DIN, SCLK - Standard 3-wire interface pins. DCEN - Selects Stand-Alone Mode or Daisy-Chain Mode. SDO - Data Out pin for Daisy-Chain Mode. Figures 3 and 4 show the timing diagram for a serial write to the AD5380 in both Stand-Alone and Daisy-Chain Mode. The 24-bit data word format for the serial interface in shown in Figure 9 below.
MSB A /B R/W W A5 A4 A3 A 2 A 1 A 0 REG1 REG0 LSB DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 9 . AD5380, 40-Channel, 14-Bit DAC Serial Input Register Configuration
A/B When Toggle mode is enabled this selects whether the data write is to the A or B register, with Toggle disabled this bit should be set to zero to select the A data register. R/W is the Read or Write control bit. A5-A0 are used to Address the input channels . REG1 & REG0 Select the register to which data is written as outlined in Table 1. DB13-DB0 Contain the input data word. X is a dont care condition.
Stand-Alone Mode
By connecting DCEN (Daisy-Chain Enable) pin low, Stand-Alone Mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC except for a falling edge are ignored until 24 bits are clocked in. Once 24 bits have been shifted in, the SCLK is ignored. In order for another serial transfer to take place the counter must be reset by the falling edge of SYNC.
Daisy-Chain Mode
For systems which contain several devices the SDO pin may be used to daisy-chain several devices together. This daisychain mode can be useful in system diagnostics and reducing the number of serial interface lines. By connecting DCEN (Daisy-Chain Enable) pin high, the Daisy-Chain Mode is enabled. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 REV. PrF 09/2003 -23-
PRELIMINARY TECHNICAL DATA AD5380
clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multi-device interface is constructed. 24 clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 24N where N is the total number of AD538X devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy-chain and prevents any further data being clocked into the input shift register. If the SYNC is taken high before 24 clocks are clocked into the part this is considered as a bad frame and the data is discarded. The serial clock may be either a continuous or a gated clock. A continuous SCLK source can only be used if it can be arranged that SYNC is held low for the correct number of clock cycles. In gated clock mode a burst clock containing the exact number of clock cycles must be used and SYNC taken high after the final clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W=1, the bits A5-A0 in association with bits REG1 and REG0 selects the register to be read. The remaining data bits in the write sequence are dont cares. During the next SPI write the data appearing on the SDO output will contain the data from the previously addressed register. For a read of a single register the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in figure 10 shows the readback sequence. For example, to readback the M register of channel 0 on the AD5380 the following sequence should be implemented. Firstly write 404XXX Hex to the AD5380 input register. This configures the AD5380 for read mode with M register of channel zero selected. Note all the data bits DB13 to DB0 are dont cares. Follow this with a second write, a NOP condition, 000000 Hex, during this write the data from the M register is clocked out on the DOUT line, ie data clocked out will contain the data from the M register in bits DB13 to DB0, and the top 10 bits contain the address information as previously written. In readback mode the SYNC signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. Is the SCLK idles high between the write and read operations of a readback operation then the first bit of data is clocked out on the falling edge of SYNC.
SCLK
24
48
SYNC
DIN
DB23 Input Word Specifies Register to be Read
DB0
DB23' NOP Condition DB23
DB0'
SDO UNDEFINED
DB0 Selected Register Data Clocked out.
Figure 10 . AD5380, Serial Readback Operation
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I2C SERIAL INTERFACE The AD5380 features an I2C compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5380 and the master at rates up to 400kHz. Figure 5,6 and shows the 2-wire interface timing diagrams that incorporate three different modes of operation. In selecting the I2C operating mode firstly configure serial operating mode (SER/PAR=1) and then select I2C mode by configuring the SPI/I2C pin to a logic 0. The device is connected to this bus as slave devices (i.e., no clock is generated by the AD5380/81/82/83). The AD5380 has a 7-bit slave address 1010 1AD1AD0. The 5 MSBs are hard coded and the two LSBs are determined by the state of the AD1 AD0 pins.The facility to hardware configure AD1 and AD0 allows four of these devices to be configured on the bus. I2C Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP Conditions. Both SDA and SCL are pulled high by the external pull-up resistors when the I2C bus is not busy. START and STOP Conditions A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition from the master signals the beginning of a transmission to the AD5380. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. Repeated START Conditions A repeated START (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The AD5380 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication. AD5380 Slave Addresses A bus master initiates communication with a slavedevice by issuing a START condition followed by the 7bit slave address. When idle, the AD5380 waits for a START condition followed by its slave address. The LSB of the address word is the Read/Write (R/W) bit. The AD538X devices are receive devices only and when communicating with these R/W = 0. After receiving the proper address 1010 1AD1AD0 , the AD5380 issues an ACK by pulling SDA low for one clock cycle. The AD5380 has four different user programmable addresses determined by the AD1 and AD0 bits. Write Operation There are three specific modes in which data can be written to the AD5380 family of DACs. 4-Byte Mode. When writing to the AD5380 DACs, the user must begin with an address byte (R/W = 0) after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte, this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Two bytes of data are then written to the DAC as shown in Figure 11. A STOP condition follows. This allows the user to update a single channel within the AD5380 at any time and requires 4 bytes of data to be transferred from the master.
SCL
SDA START COND BY MASTER
1
0
1
0
1
AD1
AD0
R/W
0 ACK MSB BY AD538X
0
A5
A4
A3
A2
A1
A0 ACK BY AD538X
ADDRESS BYTE
POINTER BYTE
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X STOP COND BY MASTER
Figure 11 . 4-Byte AD5380, I2C Write Operation
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PRELIMINARY TECHNICAL DATA AD5380
3-Byte Mode Three byte mode allows the user update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is only required once and subsequent channel updates require the pointer byte and the data bytes. In three byte mode the user begins with an address byte (R/W = 0) after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte, this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated. If a STOP condition is not sent following the data bytes another channel can be updated by sending a new pointer byte followed by the data bytes. This mode only requires 3-bytes to be sent to update any channel once the device has been initially addressed and reduces the software overhead in updating the AD5380 channels. A STOP condition at any time exits this mode. Figure 12 shows a typical configuration.
SCL
SDA START COND BY MASTER
1
0
1
0
1
AD1
AD0
R/W
0 MSB ACK BY AD538X
0
A5
A4
A3
A2
A1
A0 ACK BY AD538X
ADDRESS BYTE
POINTER BYTE FOR CHANNEL "N"
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
DATA FOR CHANNEL "N" SCL
SDA
0 MSB
0
A5
A4
A3
A2
A1
A0 ACK BY AD538X
POINTER BYTE FOR CHANNEL "NEXT CHANNEL"
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X STOP COND BY MASTER
DATA FOR CHANNEL "NEXT CHANNEL"
Figure 12 . 3-Byte AD5380, I2C Write Operation
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2-Byte Mode Two byte mode allows the user update channels sequentially following initialization of this mode. The device address byte is only required once and the pointer address pointer is configured for auto increment or burst mode. The user must begin with an address byte (R/W = 0) after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (FF Hex) which initiates the burst mode of operation. The address pointer initializes to channel zero and the data following the pointer is loaded to channel 0, the address pointer automatically increments to the next address. The REG0 and REG 1 bits in the data byte determine the register to be updated. In this mode, following the initialization only the 2-data bytes are required to update a channel, the channel address automatically increments from address 0 to channel 39 and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A STOP condition at any time exits this mode. Toggle mode of operation is not supported in 2-Byte Mode. Figure 13 shows a typical configuration.
SCL
SDA START COND BY MASTER SCL
1
0
1
0
1
AD1
AD0
R/W
A7=1
A6=1
A5=1
A4=1
A3=1
A2=1
A1=1
A0=1 ACK BY Converter
ADDRESS BYTE
ACK MSB BY Converter
POINTER BYTE
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY AD538X
CHANNEL 0 DATA SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY Converter
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY Converter
CHANNEL 1 DATA
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB ACK BY Converter
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY Converter STOP COND BY MASTER
CHANNEL N DATA FOLLOWED BY STOP
Figure 13 . 2-Byte AD5380, I2C Write Operation
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PRELIMINARY TECHNICAL DATA AD5380
AD5380 PARALLEL INTERFACE
The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 5 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins:
CS Pin
Active low device select pin.
WR Pin On the rising edge of WR , with CS low, the address on pins A5-A0 are latched and data present on the data bus is loaded into the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination register of the data being written to the AD5380. See Table I.
A5-A0 Pins
Each of the 40 DAC channels can be addressed individually.
DB13-DB0 Pins
The AD5380 accepts a straight 14-bit parallel word on DB13-DB0 where DB13 is the MSB and DB0 is the LSB.
MICROPROCESSOR INTERFACING
Parallel Interface
CONTROLLER/ DSP PROCESSOR* D15 DATA BUS D0 UPPER BITS OF ADDRESS BUS ADDRESS DECODE
AD538X
REG1 REG0 D13 D0 CS LDAC
A5 A4 A3 A2 A1 A0 R/W
A5 A4 A3 A2 A1 A0 WR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14 . AD5380 -Parallel Interface
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PRELIMINARY TECHNICAL DATA AD5380
The AD5380 can be interfaced to a variety of 16-bit microcontrollersor DSP processors. Figure 14 shows the AD5380 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0 to A5 on the AD5380 as shown. The upper address lines are decoded to provide a CS, LDAC signals for the AD5380. The fast interface timing of the AD5380 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure 14.
AD5380 to MC68HC11
DVDD
AD538X PIC16C6X/7X
SER/PAR RESET SDI/RC4 SDO
SDO/RC5
DIN
SCK/RC3 RA1
SCLK SYNC SPI/I2C
The Serial Peripheral Interface is configured for Master Mode larity Bit (CPOL) = 0 and the = 1. The SPI is configured by Register (SPCR)--see 68HC11
(SPI) on the MC68HC11 (MSTR = 1), Clock PoClock Phase Bit (CPHA) writing to the SPI Control User Manual. SCK of
AD538X
SER/PAR
DVDD
Figure 16 . AD5380 -PIC16C6X/7X Interface
AD5380 to PIC16C6x/7x
MC68HC11
RESET
MISO
SDO
MOSI
DIN
SCK PC7
SCLK SYNC SPI/I2C
The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register(SSPCON). See user PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5380. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations are needed depending on the mode. Figure 16 shows the connection diagram.
DVDD
Figure 15 . AD5380 -MC68HC11 Interface
the 68HC11 drives the SCLK of the AD5380, the MOSI output drives the serial data line (DIN) of the AD5380 and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5380, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.
8XC51
DVDD
AD538X
SER/PAR RESET
RxD
SDO
DIN
TxD P1.1
SCLK SYNC SPI/I2C
Figure 17 . AD5380 - 8051 Interface
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PRELIMINARY TECHNICAL DATA AD5380
AD5380 to 8051 POWER SUPPLY DECOUPLING
The AD5380 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode serial data enters and exits through RxD and a shift clock is output on TxD. Figure 17 shows how the 8051 is connected to the AD5380. Because the AD5380 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5380 requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.
DVDD
AD538X ADSP2101/ ADSP2103
DR SER/PAR RESET SDO
DT
DIN
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5380 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5380 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (AVDD, AVCC) it is recommended to tie those pins together. The AD5380 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5380 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on VIN and REFIN lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
SCK TFS RFS
SCLK SYNC SPI/I2C
Figure 18 . AD5380 -ADSP2101/ADSP3103 Interface
AD5380 to ADSP2101/2103
Figure 18 shows a serial interface between the AD5380 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
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PRELIMINARY TECHNICAL DATA AD5380
APPLICATIONS INFORMATION AD5380 Monitor Function
The AD5380 contains a channel monitor function consisting of a multiplexer addressed via the interface allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode Vout 39 becomes the MON_OUT pin, the pin to which all monitored signals are routed. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. Table X contains the decoding information required to route any channel to the MON_OUT pin. Selecting channel address 63 tristates the MON_OUT pin. Figure 19 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead sot package. The controller output port selects the channel to be monitored and the input port reads the converted data from the ADC.
AVCC VOUT 0 DIN SYNC SCLK OUTPUT PORT
. . . . . .
VOUT 38
AD5380
VOUT 39/MON_OUT VIN
AVCC
AD7476 CS
GND AGND DAC_GND SIGNAL GND SCLK SDATA INPUT PORT
CONTROLLER
Figure 19. Typical Channel Monitoring Circuit Toggle Mode Function The toggle mode function allows an output signal to be generated using the LDAC control signal that switches between two DAC data registers. This function is configured using the SFR control register as follows. A write with REG1=REG0=0, A5-A0=001100 specifies a control register write. The toggle mode function is enabled in groups of 8channels using bits CR6 to CR2 in the control register. See AD5380 control register description. Figure 20 shows a block diagram of the toggle mode implementation. Each of the 40 DAC channels on the AD5380 contain an A and a B data register. Note, the "B" registers can only be loaded when Toggle mode is enabled. The sequence of events when configuring the AD5380 for toggle mode of operation is as follows: i) Enable Toggle Mode for the required channels via the Control Register ii) Load Data to A registers iii) Load Data to B registers. iv) Apply LDAC. The LDAC is used to switch between the "A" and "B" registers in determining the analog output. The first LDAC configures the output to reflect the data in the "A" registers. This mode offers significant advantages if the user wants to generate a square wave at the output of all 40 channels as might be required to drive a liquid crystal based variable optical attenuators. In this case the user writes to the control register and enables the toggle function by setting CR6 to CR2=1 enabling the five groups of 8 for toggle mode operation. The user must then load data to all 40 "A" registers and "B" registers. Toggling the LDAC will set the output values to reflect the data in the A and B registers and the frequency of the LDAC will determine the frequency of the squarewave output. Toggle mode is disabled via the control register, the first LDAC following the disabling of the toggle mode will update the outputs with the data contained in the "A" registers.
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PRELIMINARY TECHNICAL DATA AD5380
DATA REGISTER A
DAC REGISTER
14-BIT DAC
VOUT
INPUT DATA
INPUT REGISTER
DATA REGISTER B
A/B
LDAC CONTROL INPUT
Figure 20. Toggle Mode Function
Thermal Monitor Function The AD5380 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. The short circuit current of each output amplifier is typically 40mA. Operating the AD5380 at 5V leads to a power dissipation of 200mW / shorted amplifier. With 5 channels shorted this leads to an extra watt of power dissipation. For the 100-lead LQFP the Qja is typically 44C/W. The thermal monitor is enabled by the user via CR8 in the control register. The output amplifiers on the AD5380 are automatically powered down if the die temperature exceeds 130C approx. After a thermal shutdown has occured the user can re-enable the part by executing a soft power up if the temperature has dropped below 130C or by turning off the thermal monitor function via the control register.
AD5380 in a MEMS Based Optical Optical Switch
MEMS based optical switches have a requirement for high resolution DACs in their feedforward control path that offer high channel density with 14-bit monotonic behaviour. The AD5380, 40-channel, 14-bit DAC in a 100lead LQFP package satisifies these requirements. In the circuit shown in Figure 19, the 0V-5V outputs of the AD5380 are amplified to achieve an output range of 0V-200V used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors. The sensor outputs are multiplexed into a high resolution ADC in determining the mirror position. The control loop is closed and driven by an ADSP-21065L, a 32-bit SHARC(R) DSP with an SPI-compatible SPORT interface. It writes data to the DAC, controls the multiplexer, and reads data from the ADC via the serial interface.
+5V 0. 01uF R EFO U T R EFI AV D D N VO 1 14- i D AC Bt O ut putR ange 0200V
. . . .
14- i D AC Bt
. . . .
VO 40
G =50
. . . .
Act or uat s For M EM S M ir r or Ar ay r
8- hannelAD C C ( 7856) AD Sensor + M uli exer tpl OR Si e C hannel ngl AD C ( 7671) AD
G =50
AD 5380
AD SP21065L
Figure 19 . AD5380 in a MEMS based Optical Switch
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PRELIMINARY TECHNICAL DATA AD5380
Optical Attenuators
The AD5380 based on its high channel count, high resolution, monotonic behaviour and high level of integration is ideally targetted at optical attenuation applications used in dynamc gain equilizers, variable optical attenuators (VOA) and Optical Add-Drop Mutliplexers (OADM). In these applications each wavelength is individually extracted using an arrayed wavequide and its power monitored using a photo-diode, transimpedance amplifier and ADC in a close loop control system. The AD5380 controls the optical attenuator for each wavelength ensuring that the power is equilized in all wavelengths before being multiplexed onto the fibre. This prevents information loss and saturation from occurring at amplification stages further along the fibre.
AD D PO R TS DRO P PO R TS
O ptcal i Sw ich t
l1
DW DM I N FI R E B
Phot di o- odes At enuat t or At enuat t or DW DM O UT AW G FI R E B
l2
AW G . . . . . .
. . . At enuat t or At enuat t or .... ....
. . .
ln1 ln
AD 5380, 40- hannel C , 14- i D AC Bt
TI LO G AM P A/ ( 8304/ AD 5) N : M uli exer 1 tpl AD G 731 ( 1 M U X) 40:
C O N TR O LLER
16- I AD C BT
AD 7671 ( 5V,1M SPS) 0-
Figure 20 . OADM using the AD5380 as part of an Optical Attenuator
Utilizing the AD5380 FIFO
The AD5380 FIFO mode optimizes total system update rate in applications where a large number of channels need to be updated. FIFO mode is only available when the parallel interface mode is selected. The FIFOEN pin is used to enable the FIFO. The status of the FIFOEN pin is sampled during the initialisation sequence, therefore the FIFO status can only be changed by resetting the device. An example of where a large number of channels need to be updated in a short period of time would be in a telescope that provides for the cancellation of atmospheric distortion. In these systems as many as 400channels need to be updated in a window of 40us. 400 channels necessitates the use of 10* AD5380 devices. With FIFO mode enabled the data write cycle time is 40ns, therefore each group consisting of 40 channels can be fully loaded 1.6us. In FIFO mode a complete group of 40 channels will update in 14.4us. Therefore the time taken to update all 400channels will equate to 14.4us +9*1.6us = 28.8us. Figure 21 shows a graphical view of the FIFO operation scheme.
GROUP A Chnls 0-39 GROUP B Chnls 40-79 GROUP C Chnls 80-119 GROUP D Chnls 120-159 GROUP E Chnls 160-199 GROUP F Chnls 200-239 GROUP G Chnls 240-279 GROUP H Chnls 280-319 GROUP I Chnls 320-359 GROUP J Chnls 360-399
1.6us
FIFO DATA LOAD Group A
1.6us
FIFO DATA LOAD Group B
1.6us
FIFO DATA LOAD Group J
14.4us
Output Update Time for Group A
14.4us 14.4us
Output Update Time for Group B Output Update Time for Group J
Time to Update 400 Channels = 28.8us
Figure 21. Using FIFO mode 400 Channels Updated in under 30us.
REV. PrF 09/2003 -33-
PRELIMINARY TECHNICAL DATA AD5380
OUTLINE DIMENSIONS
ST100 (100 Lead LQFP) Package Dimensions
0.640 (16.25) SQ 0.620 (15.75) 0.555 (14.10) SQ 0.547 (13.90)
10 0 1 76 75
0.061 (1.55) 0.049 (1.25) 0.026 (0.65) 0.014 (0.35) SEA TIN G PLAN E 12 TYP
TOP V IEW
(P IN S D O W N )
0.004 (0.102) M AX LEAD COPLANARITY 0 10
25
6 4 0.007 (0.177) 0.003 (0.077)
26
51 50
0.020 (0.50) BSC
0.012 (0.20) 0.004 (0.10)
-34-
REV. PrF 09/2003

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